View SI3402-C_8999172.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.0 12/16 copyright ? 2016 by silicon laboratories SI3402-C SI3402-C f ully - integrated ieee 802.3-c ompliant p o e pd i nterface and l ow -emi s witching r egulator features applications description the si3402 integrates all power management and control functions required in a power-over-ethernet (poe) powered device (pd) application. the si3402 converts the high voltage supplied over the 10/100/1000base-t ethernet connection into a regulated, low-voltage output supply. the optimized architecture of the si3402 minimizes the solution footprint, reduces external bom cost, and enables the use of low-cost external components while maintaining high performance. the si3402 integrates the required diode bridges and transient surge suppressor, thus enablin g direct connection of the ic to the ethernet rj-45 connector. the sw itching power fet and all associated functions are also integrated. the integrated switching regulator supports isolated (flyback) and non-isolated (buc k) converter topologies. the si3402 supports ieee 802.3 type 1 (class 3 and below) powered device applications. standard external resistors connected to the si3402 provide the proper ieee 802.3 signatures for the detection functi on and programming of the requested power class. startup circuits ensure we ll-controlled initial operation of both the hotswap switch and the voltage regulator. the si3402 is available in a low- profile, 20-pin, 5 x 5 mm qfn package. the SI3402-C is a pin-compatible replacement of the obsolete si3402-a. pcb layouts designed for si3402-a can be reused with SI3402-C, but some component value changes are required. the SI3402-C?s functionality is similar to that of the si3402-b but without the requirement to make a connection betw een the ethernet jack and ct1, ct2, sp1, or sp2 pins when bypassing the integrated diode bridge with external schottky diodes. further, ploss func tionality is removed from the SI3402-C. ? pin-compatible replacement for the obsolete si3402-a ? ieee 802.3 standard-compliant solution, including pre-standard (legacy) poe support ? highly-integrated ic enables compact solution footprints ?? minimal external components ?? integrated diode bridges and transient surge suppressor ?? integrated switching regulator controller with on-chip power fet ?? integrated dual current-limited hotswap switch ? programmable classification circuit ? incorporates switcher emi- reduction techniques. ? supports non-isolated and isolated switching topologies ? comprehensive protection circuitry ?? transient overvoltage protection ?? undervoltage lockout ?? thermal shutdown protection ?? foldback current limiting ? allows external schottky diode bypass of integrated diode bridges without requiring ct/sp pin connection ? low-profile 5 x 5 mm 20-pin qfn ? rohs-compliant ? voice over ip telephones and adapters ? wireless access points ? security cameras ? point-of-sale terminals ? internet appliances ? network devices ? high power applications ordering information: see page 18. pin assignments 5x5mm qfn (top view) note: original pin names shown for compatibil- ity reasons, but ssft, isossft, vposs, and vss1 are not internally connected. erout ssft* rdet hso rcl sp1 sp2 vposf ct1 nc isossft* vdd 5678 9 10 1 2 3 4 11 12 13 14 vneg vssa vposs vss1 swo vss2 fb vneg (pad) ct2 1516 20 19 18 17
SI3402-C 2 rev. 1.0 functional block diagram detection & classification hotswap switch & c urrent lim it hotswap control & common bias pwm control and emi limiting s w itching fet rectification & protection ct1 ct2 sp1 sp2 vposf vneg rdet rcl hso vdd ploss vss1* swo erout fb ssft* isossft* vss2 vposs* vssa note : original pin names shown for compatibility reasons, but ssft, isossft, vposs, and vss1 are not internally connected.
SI3402-C rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schemati cs* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2. pd hotswap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. isolated and non- isolated application topologie s . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4. switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5. output voltage and therma l considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. recommended land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. device marking diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SI3402-C 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions description symbol min typ max units |ct1 ? ct2| or |sp1 ? sp2| vport 2.8 ? 57 v ambient operating temperature ta ?40 25 85 c note: unless otherwise noted, all voltages referenced to vneg. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typi cal values apply at nominal supply voltage and ambient temperature unless otherwise noted. table 2. absolute maximum ratings 1 type description rating unit voltage ct1 to ct2 2 ?100 to 100 v sp1 to sp2 2 ?100 to 100 v vpos ?0.7 to 100 v hso ?0.7 to 100 v v ss1 , v ss2 , or v ssa ?0.7 to 100 v v ss1 to v ss2 or v ssa ?0.3 to 0.3 v swo 3 ?0.7 to 100 v rdet ?0.7 to 100 v vdd to vss1, vss2, or vssa ?0.3 to 5.5 v peak current ct1, ct2, sp1, sp2 2 ?5 to 5 a vpos 2 ?5 to 5 a dc current 4 ct1,ct2,sp1,sp2 ?0.2 to 0.2 a ambient temperature storage ?65 to 150 c operating ?40 to 85 c notes: 1. unless otherwise noted, all voltages referenced to vneg . permanent device damage may occur if the maximum ratings are exceeded. functional operation should be restricted to those conditions specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability. 2. si3402 provides internal protection from certain transient surge voltages on these pins. please refer to ?an1050: SI3402-C poe pd controller design guide? for details. 3. swo is referenced to v ss2 . 4. higher dc current is possible in the application, but only ut ilizing external bridge diodes. refer to ?an1050: SI3402-C poe pd controller design guide? for more information.
SI3402-C rev. 1.0 5 table 3. electrical characteristics parameter description min typ max unit vport detection 1 2.7 ? 11 v classification 14 ? 22 uvlo turn-off for rising volt- ages (switching regulator turns on) ?3742 uvlo turn-on for falling volt- ages (switching regulator turns off) 30 32 36 integrated transient surge clamp voltage 2 ?100? input offset current vport < 10 v ? ? 10 a diode bridge leakage vport = 57 v ? ? 25 a iport classification 3 class 0 0 ? 4 ma class 1 9 ? 12 class 2 17 ? 20 class 3 26 ? 30 iport operating current 4 37 v < vport < 57 v ? 2 3.1 ma current limit 5 inrush ? 140 ? ma operating 470 ? 680 ma hotswap fet on-resistance 37 v < vport < 57 v 1 ? 3 ? switcher frequency ? 350 ? khz maximum switcher duty cycle ? 50 75 % switcher output transient voltage 6 ??100 v switching fet on-resistance 0.3 0.5 1.3 ? switching fet peak current ? ? 2.4 a regulated feedback @ pin fb 7 dc avg. 1.30 1.35 1.40 v notes: 1. assumes use of internal diode bridge or external schottky bridge. 2. transient surge as defined in ieee 802.3 is applied across ct1-ct2 or sp1-sp2. 3. the classification currents are g uaranteed only wh en recommended rclass resistors ar e used, as specified in ta b l e 7 . 4. iport includes full operating current of switching regulator controller. 5. the pd interface includes dual-level input current limit. at turn-on, before the hso load capacitor is charged, the current limit is set at the inrush level. after the capa citor has been charged within ~0.4 v of vneg, the operating current limit is engaged. this higher current limit remains acti ve until the uvlo lower limit has been tripped or until the hotswap switch is sufficiently current-limited to cause a foldback of the hso voltage. for more information, see "3.2.5. dual input current limit and switcher turn-on" on page 11. 6. for switcher output transient voltage control with isolated ap plications, please use a voltage snubber circuit. refer to ?an1050: SI3402-C poe pd controller design guide? fo r additional guidance on voltage snubber circuit design. 7. applies to non-isolated applications only.
SI3402-C 6 rev. 1.0 vdd accuracy 0-5 ma and uvlo off (switching regulator on) 4.5 ? 5.5 v thermal shutdown junction temperature ? 160 ? oc thermal shutdown hysteresis ? 25 ? oc table 4. total power dissipation description test condition min typ max unit power dissipation vport = 50 v, v out =5v, 2a ?1.2? w power dissipation* vport = 50 v, v out = 5 v, 2 a w/ diode bridges bypassed ?0.7? w *note: it is recommended that the on-chip diode bridges be by passed when input power requirements are >10 w or in thermally-constrained applications. for more information , see ?an1050: SI3402-C poe pd controller design guide?. table 5. package thermal characteristics parameter symbol test condition typ unit thermal resistance (junction to ambient) ? ja still air; assumes a minimum of nine thermal vias are connected to a 2 in 2 heat spreader plane for the package ?pad? node (vneg). 45.1 c/w table 3. electrical characteristics (continued) parameter description min typ max unit notes: 1. assumes use of internal diode bridge or external schottky bridge. 2. transient surge as defined in ieee 802.3 is applied across ct1-ct2 or sp1-sp2. 3. the classification currents are g uaranteed only wh en recommended rclass resistors ar e used, as specified in ta b l e 7 . 4. iport includes full operating current of switching regulator controller. 5. the pd interface includes dual-level input current limit. at turn-on, before the hso load capacitor is charged, the current limit is set at the inrush level. after the capa citor has been charged within ~0.4 v of vneg, the operating current limit is engaged. this higher current limit remains acti ve until the uvlo lower limit has been tripped or until the hotswap switch is sufficiently current-limited to cause a foldback of the hso voltage. for more information, see "3.2.5. dual input current limit and switcher turn-on" on page 11. 6. for switcher output transient voltage control with isolated ap plications, please use a voltage snubber circuit. refer to ?an1050: SI3402-C poe pd controller design guide? fo r additional guidance on voltage snubber circuit design. 7. applies to non-isolated applications only.
SI3402-C rev. 1.0 7 2. typical application schematics* *note: these are simplified schematics. see ?an1050: SI3402-C poe pd controller design guide? for more information. figure 1. schematic?non-isolated buck topology* figure 2. schematic?isolated flyback topology si3402c rcl rdet ct1 ct2 sp1 sp2 vposf ssft vdd isossft vposs vneg hso vss1 vss2 vssa swo fb erout rj-45 vout + - 1 2 3 4 5 6 7 8 to ethernet phy si3402c rcl rdet ct1 ct2 sp1 sp2 vposf ssft vdd isossft vposs vneg hso vss1 vss2 vssa swo fb erout vout + - rj-45 1 2 3 4 5 6 7 8 to ethernet phy
SI3402-C 8 rev. 1.0 3. functional description the si3402 consists of two major func tions: a hotswap controller/interface and a complete pulse-width-modulated switching regulator (cont roller and power fet). 3.1. overview the hotswap interface of the si3402 pr ovides the complete front end of an ieee 802.3 -compliant pd. the si3402 also includes two full diode bridges, a transient voltage su rge suppressor, detection circ uit, classification current source, and dual-level hotswap current limiting switch. this high level of integration enables direct connection to the rj-45 connector, simplif ies system design, and provides significant advantages for reliab ility and protection. the si3402 requires only four standard external component s (detection resistor, optional classification resistor, load capacitor, and input capacitor) to create a fully i eee 802.3-complia nt interface. the si3402 integrates a complete pulse-width modulated sw itching regulator that includes the controller and power fet. the switching regulator utilizes a constant frequency pu lse-width modulated cont roller optimized for all possible load conditions in poe applications. the regulato r integrates a low on-resistance (ron) switching power mosfet that minimizes power dissipation, increases over all regulator efficiency, an d simplifies system design. an integrated error amplifier, pr ecision reference, and soft-s tart feature pr ovide the flexibility of using a non-isolated buck regulator topology or an isolated flyback regulator topology. the si3402 is designed to operate with both ieee 802.3-compliant power sourci ng equipment (pse) and pre- standard (legacy) pses that do not a dhere to the ieee 802.3 specified inrush curr ent limits. the si3402 is compatible with compliant and legacy pses because it uses two levels for the hotswap current limits. by setting the initial inrush current limit to a low level, a pd based on the si3402 minimizes the current drawn from either a compliant or legacy pse during startup. after powering up, the si3402 automatically swit ches to a higher-level current limit, thereby allowing the pd to consume up to 12 .95 w (the max power a llowed by the ieee 802.3 specification). excessive power cycling or short circui t faults will engage the th ermal overload protection to prevent the on-chip power mosfets from exceeding their safe and reliable operating ranges. the switching regulator power mosfet has been designed and sized to withstand the high peak currents created when converting a high-voltage, low- current supply into a low-voltage, high-current supply.
SI3402-C rev. 1.0 9 3.2. pd hotswap controller the si3402 hotswap controller changes its mode of oper ation based on the input voltage applied to the high- voltage supply inputs (ct1, ct2, sp1, sp2), the ieee 802.3 -defined modes of operation, and internal controller requirements. table 6 defines the modes of operation for the hotswap interface. figure 3 provides a representation of the input lines , protection, and hotswap circuits on the si3402. figure 3. input lineside and hotswap block diagram table 6. hotswap interface modes input voltage (|ct1-ct2| or |sp1-sp2|) si3402 mode 0 to 2.7 v inactive 2.7 to 11 v detection signature 11 to 14 v transition region 14 to 22 v classification signature 22 to 42 v transition region 37 up to 57 v switcher operating mode (hysteresis limit based on rising input voltage) 57 down to 32 v switcher operati ng mode (hysteresis limit based on falling input voltage) diode bridges and protection detection control on off vpos vneg ct1/sp1 ct2/sp2 ~2.7v rdet classification control on off rcl central bias bandgap ref current limit hi/lo hotswap control on off ~37v (rising) ~32v (falling) switcher startup & bias hso bias voltages ~11v ~14v ~22v
SI3402-C 10 rev. 1.0 3.2.1. rectification diode bridges and surge suppressor the ieee 802.3 specification defines the input voltage at the rj-45 connector of t he pd with no reference to polarity. in other words, the pd must be able to accept power of either polarity at each of its inputs. this requirement necessitates the use of two sets of diode br idges, one for the ct1 and ct2 pins and one for the sp1 and sp2 pins to rectify the voltage. furthermore, the stan dard requires that a pd withstand a high-voltage transient surge as defined in the ieee 802.3 specification. typi cally, the diode bridge and the surge suppressor have been implemented externally, adding cost an d complexity to the pd system design. the diode bridge* and the surge suppressor have been integrated into the si3402, thus reducing system cost and design complexity. *note: it is recommended that the on-chip diode bridges be bypassed when input power requirements are >10 w or in thermally-constrained applications. for more information, see ?an1050: SI3402-C poe pd controller design guide?. when bypassing the on-chip, integrated diode bridges wit h external diodes, note that schottky diodes with low forward voltage drop are required. st andard (e.g. ?s1b?) type diodes ha ve high forward voltage drop and will interfere with proper device operatio n during the detection cycle. note fu rther that, when th e integrated diode bridges are bypassed, it is no t required to make connections to ct1, ct2, sp1, or sp2. integration of the surge suppressor enables optimization of the clamping voltage and guarantees protection of all connected circuitry. as an added benefit, the transient surge suppressor, when tripped, actively disables the hotswap interface and switching regulator, preventing downstream circuits from encountering the high-energy transients. 3.2.2. detection in order to identify a device as a va lid pd, a pse will apply a voltage in the range of 2.8 to 10 v on the cable and look for a valid signat ure resistance. the si34 02 will react to voltages in this range by connecting the external 24.3 k ? detection resistor between vpos and vneg. this ex ternal resistor and internal low-leakage control circuitry create the proper sign ature to alert the pse that a valid pd has been detected and is ready to have power applied. the internal hotswap switch is disabled during this time to prevent the s witching regulator and attached load circuitry from generating errors in the detection signature. since the si3402 integrates the diode bridges, the ic compensates for the vo ltage and resistance effects of the diode bridges. 3.2.3. classification once the pse has detected a valid pd, the pse may classify the pd for one of five po wer levels or classes. a class is based on the expected power co nsumption of the powered device. an external resistor sets the nominal class current that can then be read by the pse to determine the proper power require ments of the pd. when the pse presents a fixed voltage between 15.5 v and 20.5 v to the pd, the si3402 asserts the class current from vpos through the rcl re sistor. the resistor values associated with each class are shown in table 7. table 7. class resistor values class usage peak power levels nominal class current rcl resistor (1%, 1/16 w) 0 default 0.44 to 12.95 w < 4 ma > 681 ? (or open circuit) 1 optional 0.44 to 3.84 w 10.5 ma 140 ? 2 optional 3.84 to 6.49 w 18.5 ma 75.0 ? 3 optional 6.49 to 12.95 w 28 ma 48.7 ?
SI3402-C rev. 1.0 11 3.2.4. under voltage lockout the si3402 incorporates an undervoltage lockout (uvlo) circuit to monitor the line voltage and determine when to apply power to the integrated switching regulator. before power is applied to the switching regulator, the hotswap switch output (hso) pin is high-impedance and typically follows vpos as the inpu t is ramped (due to the discharged switcher supply capacitor). when the input vo ltage rises above the uvlo turn-off voltage (typicall 37 v), several things happen: 1. the si3402 begins to turn on the internal hotswap power mosfet (hssw). 2. the switcher supply capacitor begins to charge up under the current limit control of the si3402. 3. the hso pin transitions from vpos to vneg. the si3402 includes hysteretic uvlo circuits to maintain power to the load until the input voltage falls below the uvlo turn-on voltage (typically 32 v). once the input volt age falls below that threshold, the hssw is turned off (note that the switching regulator also turns off). figure 4 provides a visual depiction of the uvlo feature. figure 4. uvlo behavior and threshold voltages 3.2.5. dual input current limit and switcher turn-on the si3402 implements dual input current limits. while th e hssw is charging the switcher supply capacitor, the si3402 maintains a low curr ent limit. the switching regulator is disa bled until the voltage across the hssw becomes sufficiently low, indicating the switcher supply capacitor is al most completely charged. when this threshold is reached, the switcher is activat ed, and the hotswap current limit is increased. the si3402 stays in the high-level input current limit mode until the input voltage drops below the uvlo turn-on threshold or excessive power is dissipated in the hotswap switch. an additional feature of the current limit circuitry is curren t limiting in the event of a fault condition. when the current limit is switched to the high er level, 470 ma of current can be drawn by the pd. should a fault cause more than this current to be consumed, the hssw goes into a temporar y 10 ma current limit mode and turns off the switcher. after 90 ms have elapsed, and if the switcher supply capacitor is recharged, the hssw turns back on in the 470 ma limit mode, and enables the switcher. pd input voltage regulator off 32v 37v regulator on typical thresholds: uvlo on uvlo on uvlo off uvlo off
SI3402-C 12 rev. 1.0 3.3. isolated and non-is olated application topologies power over ethernet (poe) applications fall into two br oad categories, isolated and non-isolated. non-isolated systems can be used when the powered device is self-contained and does not provide external conductors to the user or another application. non-isolated applications include wireless access points and security cameras. in these applications, there is no explicit need for dc isol ation between the switching regulator output and the hotswap interface. an isolated system must be used when the powered device interfaces with other self-powered equipment or has external conductors accessible to the user or other applications. for proper operation, the regulated output supply of the switching regulator must no t have a dc electrical path to the hotswap interface or switching regulator primary side. isolated applications incl ude point-of-sale terminals where the user can touch the grounded metal chassis. the application determines the converter topology. an isolated applic ation will require a flyb ack transf ormer-based switching topology while a non-isolated application c an use an inductor-based buck converter topology. in the isolated case, dc isolation is achieved through a transform er in the forward path and a voltage reference plus opto- isolator in the feedback path. the application circuit shown in figure 2 is an example of such a topology. the non- isolated application in figure 1 makes use of a single indu ctor as the energy conversion element, and the feedback signal is directly supplied into the inte rnal error amplifier. as can be seen fr om the application circuits, the isolated topology has an increased number of components, thus incr easing the bill of materials (bom) and system footprint. to optimize cost and ease implementation, each applicat ion should be evaluated for its isolated or non-isolated requirements.
SI3402-C rev. 1.0 13 3.4. switching regulator figure 5 gives a representation of the switching regulator. figure 5. switching regulator block diagram 3.4.1. switcher startup the switching regulator is disa bled until the hotswap interface has both id entified itself to the pse and charged the supply capacitor needed to filter the switching regulator 's high-current transients. once the supply capacitor is charged, the hotswap controller engages the internal bias cu rrents and supplies used by the switcher. additionally, the soft-start current begins to charge the internal soft-start capacitor. ramping this voltage slowly allows th e switching regulator to bring up the regulated output voltage in a controlled manner. controlling the initial startup of the regulated volt age restrains power dissipat ion in the switching fet and prevents overshoot and ringing in the output supply voltage and pd input current. 3.4.2. switching regulator operation the switching regulator of the si3402 is a constant-frequency, pulse-width-modulated controller (pwm) integrated with switching power fets. the design is optimized for the output po wer range defined by the ieee 802.3 specification. once the hotswap interface has ensured proper turn-on of the switching regulator contro ller, the switcher is fully operational. an internal fr ee-running oscillato r and internal precision voltage re ference are fed into the pulse-width modulator. the output of the error amplifier (either intern al for non-isolated applications or external for isolated applications) is also rout ed into the pwm controller. the pwm controls the switching fet drive circuitry. a significant advantage of integrating the switching power fet onto the same monolithic ic as the swit ching regulator controller is the ability to precisely adjust the drive strength and timing, resulting in high regulator efficiency. furtherm ore, current-limiting circuitry protects the switching fet. thermal overload protection provides a secondary level of protection. the flexibility of the si3402's switchin g regulator allows the system designer to realize either the isolated or non- isolated application circuitry using a si ngle device. in operation, the integrat ion of the switching fet allows tighter control and more efficient operation than a general-purpose switching regulator coupled with a general-purpose external fet. 3.4.3. flyback snubber large voltage transients can be generated by the induct ive kick associated with the leakage inductance of the primary side of the flyback transformer used in isolated ap plications. a snubber is nece ssary to limit these voltage transients. refer to ?an1050: SI3402-C poe pd controller design guide? for more information on the snubber. switcher startup & bias pulse width modulator erout hso vref soft start switch drive fb error amplifier oscillator vdd swo vssa vss2
SI3402-C 14 rev. 1.0 3.5. output voltage an d thermal considerations the SI3402-C supports a wide range of output volt ages for ieee 802.3-comp liant class 0-3 designs. because the SI3402-C integrates the switching fet and hssw, the case temp erature of the si3402- c will depend heavily on the output power and the thermal relief provided in the pcb design. for a given output power, the integrated hssw will dissipate more power when configured for lowe r output voltages because th e current passing through it is higher. the user should closely follow the hardware design guideli nes provided in ?an1050: SI3402-C poe pd controller design guide? to ensure a robust poe pd solution, particularly for low out put voltage class 3 designs.
SI3402-C rev. 1.0 15 4. pin descriptions table 8. SI3402-C pin descriptions (top view) pin# name description 1 erout error-amplifier output and pwm input; directly connected to opto-coupler in isolated application. 2 ssft* the non-isolated soft-start function is internal on the SI3402-C. therefore, this pin is not internally con- nected. 3 vdd 5 v supply rail for switcher; provides drive for opto-coupler. 4 isossft* the isolated soft-start function is internal on the SI3402-C. therefore, this pin is not internally connected. 5 nc not connected. 6 rdet input pin for external precision detection resistor ; also used for establishing absolute current reference. 7 hso hotswap switch output; connects to vneg through hotswap switch. 8 rcl input pin for external precision classificati on resistor; float if optional rclass is unused. 9, pad vneg rectified high-voltage supply, negative rail. must be connected to thermal pad node (vneg) on package bottom. this thermal pad must be connected to vneg (pin #9) as well as a 2 in 2 heat spreader plane using a minimum of nine thermal vias. 10 sp2 high-voltage supply input from spare pair; polarity-insensitive. 11 sp1 high-voltage supply input from spare pair; polarity-insensitive. 12 vposf rectified high-voltage supply, positive rail (force node) 13 ct2 high-voltage supply input from center tap of ethernet transformer; polarity-insensitive. 14 ct1 high-voltage supply input from center tap of ethernet transformer; polarity-insensitive. 15 vssa analog ground. in new designs, vssa can be left fl oating for easier pcb layout, and vss2 used as analog ground. vssa is interna lly connected to vss2. 16 vposs* the positive rail sense node function is no longer implem ented. therefore, this pin is not internally con- nected. 17 vss1* this former negative supply rail pin is no longer impl emented. therefore, this pin is not internally con- nected. 18 swo switching transistor output; drain of switching n-fet. 19 vss2 negative supply rail for swit cher; externally tied to hso. 20 fb regulated feedback input in non-isolated application. note: * si3402-a legacy pin only, shown for compatibility and comp arison purposes. legacy components and connections for this pin are harmless and can be either retained or deleted. erout ssft* rdet hso rcl sp1 sp2 vposf ct1 nc isossft* vdd 5678 9 10 1 2 3 4 11 12 13 14 vneg vssa vposs vss1 swo vss2 fb ct2 15 16 20 19 18 17
SI3402-C 16 rev. 1.0 5. package outline figure 6 illustrates the package details for the si3402. table 9 lis ts the values for the di mensions shown in the illustration. figure 6. 20-lead quad flat no-lead package (qfn) table 9. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.25 0.30 0.35 d 5.00 bsc. d2 2.60 2.70 2.80 e 0.80 bsc. e 5.00 bsc. e2 2.60 2.70 2.80 l 0.50 0.55 0.60 l1 0.00 ? 0.10 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhb-1.
SI3402-C rev. 1.0 17 6. recommended land pattern figure 7. si3402 recommended land pattern table 10. pcb land pattern dimensions symbol min nom max p1 2.70 2.75 2.80 p2 2.70 2.75 2.80 x1 0.25 0.30 0.35 y1 0.90 0.95 1.00 c1 4.70 c2 4.70 e0 . 8 0 notes: general 1. all dimensions shown are in m illimeters (mm) unle ss otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 2x2 array of 1.2 mm square openings on 1.4 mm pitch should be used for the center ground pad. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
SI3402-C 18 rev. 1.0 7. ordering guide part number 1,2 package temp range SI3402-C-gm 20-pin qfn, pb-free; rohs compliant ?40 to 85 c notes: 1. ?x? denotes product revision. 2. add an ?r? at the end of the part number to denote tape and reel option.
SI3402-C rev. 1.0 19 8. device marking diagram figure 8. device marking diagram table 11. device marking table line # text value description 1 si3402 base part number. this is not the ?o rdering part number? since it does not contain a specific revision. refer to "7. ordering guide" on page 18 for complete ordering information. 2c - g m c = device revision c g = extended temperature range. m = qfn package. 3 tttttt trace code (assigned by the assembly subcontractor). 4 circle = 20 mils diameter (bottom-left justified) pin 1 identifier. yy assembly year. ww assembly week.
SI3402-C 20 rev. 1.0 d ocument c hange l ist revision 0.4 to revision 1.0 ? created SI3402-C data sheet using si3402-b rev 1.1 data sheet as the starting point. ? removed references to ploss, wh ich is not featured on SI3402-C. ? added notes that SI3402-C does not require pcb connec tions to ct1, ct2, sp1, or sp2 when bypassing the internal diode bridge for high-power applications.
http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa smart. connected. energy-friendly. products www.silabs.com/products quality www.silabs.com/quality support and community community.silabs.com disclaimer silicon labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon labs products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon labs shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products are not designed or authorized to be used within any life support system without the specific written consent of silicon labs. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon labs products are not designed or authorized for military applications. silicon labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc.? , silicon laboratories?, silicon labs?, silabs? and the silicon labs logo?, bluegiga?, bluegiga logo?, clockbuilder?, cmems?, dspll?, efm?, efm32?, efr, ember?, energy micro, energy micro logo and combinations thereof, "the worlds most energy friendly microcontrollers", ember?, ezlink?, ezradio?, ezradiopro?, gecko?, isomodem?, precision32?, proslic?, simplicity studio?, siphy?, telegesis, the telegesis logo?, usbxpress? and others are trademarks or registered trademarks of silicon labs. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders.

▲Up To Search▲

Price & Availability of SI3402-C

	To Download SI3402-C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .